The present invention relates generally to the field of integrated circuit devices, and, more particularly, to signal distribution circuitry used in integrated circuit devices.
Signal transmission times between respective memory devices in a memory system may differ based on the positions of the memory devices. The signal transmission times between signals following similar length paths may also differ due to skew between the signals. Differences in signal transmission times and/or skew may reduce a valid data window for determining a maximum operating frequency and may increase setup times and hold times for signals.
To compensate for skew, conventional memory devices and controllers may include a phase locked loop (PLL) or a delay locked loop (DLL). Unfortunately, this may increase the size of the memory device. Also, designing the PLL or DLL may cause difficulties in developing the memory device.
FIG. 1 is a schematic of a conventional memory system that illustrates different signal delays between modules and/or memory devices. FIG. 2 is a timing diagram that illustrates skew between signals and the reduction of a valid data window due to the skew.
Referring now to FIG. 1, a conventional memory system comprises a plurality of memory modules 11, 13, and 15 controlled by a memory controller 10. The transmission time of a signal between a memory module 11, 13, or 15 and the memory controller 10 varies according to the position of the memory module 11, 13, or 15. For example, the transmission time of a signal between the memory module 11 and the memory controller 10 is t0 and the transmission time between the memory module 15 and the memory controller 10 is t10.
Memory module 11 comprises a plurality of memory devices 21, 23, 25, and 27. The transmission time of a signal between the memory controller 10 and one of the memory devices 21, 23, 25, or 27 varies according to the position of the memory device 21, 23, 25, or 27. For example, the transmission time of a signal between the memory device 21 and the memory controller 10 is t1 and the transmission time between the memory device 27 and the memory controller 10 is t4.
Thus, the transmission time of a signal between the memory controller 10 and a memory module 11, 13, or 15 varies according to the position of the memory module. Furthermore, the transmission time of a signal between the memory controller and a memory device 21, 23, 25, or 27 varies according to the position of the memory device. Similar principles apply to memory module 13, which comprises memory devices 31, 33, 35, and 37, and memory module 15, which comprises memory devices 51, 53, 55, and 57.
Referring now to FIG. 2, time t1 illustrates a data setup time that is increased due to skew between signals and/or differences in signal transmission time between the memory controller 10 and the memory modules 11, 13, and 15 and/or the memory devices contained therein. Time t3 illustrates a data hold time that is increased due to skew between signals and/or differences in signal transmission time between the memory controller 10 and the memory modules 11, 13, and 15 and/or the memory devices contained therein. Time t2 denotes a valid data window reduced by the times t1 and t3.
In a conventional memory system, various integrated circuit memory devices, such as memory devices 21, 31, and 51, may be connected to each other and there may be differences in transmission time for signals between the memory controller 10 and the memory devices 21, 31, and 51 based on the position of the memory device 21, 31, and 51. In addition, skew may exist between signals. The differences in signal transmission time and/or skew may increase the data setup time and/or the data hold time, and may reduce the valid data window for determining the maximum operating frequency of the memory system.
To compensate for skew and/or the differences in signal transmission time, a memory device and/or a memory controller may use a PLL and/or a DLL. Unfortunately, incorporating a PLL and/or a DLL into memory systems may increase the size of the memory systems. Also, designing a PLL and/or DLL may increase the development complexity of memory systems.